| | | Top Stories — January 22, 2014 | | | | | High cost per wafer, long design cycles may delay 20nm and beyond
Handel Jones, founder and CEO of International Business Strategies (IBS), spoke at SEMI's Industry Strategy Symposium, focusing on key trends, factors impacting the growth of the industry and the migration to smaller feature dimensions. He is bullish about 2014 and industry innovation, but cautious about how quickly the industry will move to new technology nodes due to higher costs, and long design cycles. | | | Safety critical devices drive fast adoption of advanced DFT
Devices used in safety critical applications such as automobiles need be known to work and have the ability to be regularly verified. Therefore, a very high-quality test is important as well as method to perform a built-in self-test. | | | Why SOI is the future technology of semiconductors
Zvi Or-Bach, President and CEO of MonolithIC 3D, blogs that this is the "one learning" we can take away from IEDM 2013. | | | SOI: Looking back over a year of moving forward
28nm FD-SOI is ramping in volume and 14nm debuting in 2014. Adele Hars looks back at the many advancements made in 2013 in FDSOI. | | | Advances in Post-Tape Out Resource Management
Foundries, both pure-play and independent device manufacturers (IDM), rigorously compete for market share. One factor that helps them get and keep business is turnaround time (TAT). As technology nodes advance, achieving targeted production runtimes in the post-tapeout flow gets ever more challenging. | | | Solid State Technology December 2013
The latest issue of Solid State Technology features in-depth articles on atomic layer etch, FinFET options for 7 and 5nm, backside via etching of SiC and defect inspection in a 200mm fab. | | | Slideshow: 2013 IEDM Highlights
Highlights from this year's International Electron Devices Meeting (IEDM) include breakthroughs in silicon and non-silicon device technology, molecular electronics, nanotechnology, optoelectronics, MEM/NEMS, energy-related devices and bioelectronics. | | | more top stories  | | News & Features | | | | | Research Alert: Jan. 21, 2014
Natural 3D counterpart to graphene discovered; A deeper look at interfaces; Energy storage in miniaturized capacitors may boost green energy technology | | | Blog review January 21, 2014
New blogs examine how Intel is stacking up against TSMC in the foundry space, new developments in 2013 in RF-SOI and SOI FinFETs, and an overview of the 3DIC presentations from IEDM by Micron, TSMC, Tokhuku Univ., NC State and SET. | | | | more news & features | | | | | | | | Our Sponsors | | | | | | | | | | Videos/Podcasts | | | | | | Solid State Watch: January 9-16, 2014 | | |  | | | | Imec and AlixPartners to develop cost modeling solution; Semiconductor packaging materials market forecast; 2013 SEMI Award winners announced; Modest recovery for microprocessors | | | | From SEMICON West 2013: Stephen Pateras of Mentor Graphics | | |  | | | | John Blyler interview Stephen Pateras, Product Marketing Manager of Mentor Graphics | | | | More Videos/Podcasts | | | | White Papers | | | | | | RF-SOI Wafers for Wireless Applications | | The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance. | | | | DFM: What is it and what will it do? | | Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda. | | | | Via Doubling to Improve Yield | | In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area. | | | | The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions | | Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters. | | | | A Study Of Model-Based Etch Bias Retarget For OPC | | The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension. | | | | | | more white papers | | | |
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